Re: Trinity lässt sich nicht mehr wiederbeleben
Verfasst: Mo 9. Apr 2018, 10:00
Bringt leider alles nichts, der Link zu CST ist tot.
Code: Alles auswählen
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| U-Boot 2009.08-00054-g61c6265 (Jun 11 2014 - 10:49:06) CST HDx |
|------------------------------------------------------------------------------|
| Chipset information |
| Vendor: NXP Type: Shiner-IP Revision: M1 Fuses: 0015726F |
|------------------------------------------------------------------------------|
| Clock information |
| *** not available yet *** |
|------------------------------------------------------------------------------|
| Frontpanel information |
| Vendor: CST Version: 5.1 Display: none |
|------------------------------------------------------------------------------|
| Memory configuration |
| Start | End | Type | Description |
|----------+----------+---------+----------------------------------------------|
| 00000000 | 0FFFFFFF | RAM | System main memory bank #0 (256M) |
| 20000000 | 2FFFFFFF | RAM | System main memory bank #1 (256M) |
| D0000000 | D03FFFFF | S-FLASH | Eon Silicon EN25Q32 ( 4M / 64K x 64) |
| 00000000*| 1FFFFFFF*| NAND | Toshiba NAND 512MiB 3,3V 8-bit |
|------------------------------------------------------------------------------|
| Network configuration |
| MAC: LIP 6300 address: 00-C5-5C-79-31-29 |
--------------------------------------------------------------------------------
Hit any key to stop autoboot: 3
Emergency update from usb
(Re)start USB...
USB: Register 10011 NbrPorts 1
USB EHCI 1.00
scanning bus for devices... 2 USB Device(s) found
scanning bus for storage devices... 1 Storage Device(s) found
reading uldr.bin
262144 bytes read
SFC erase: offset 0x0, size 0x40000
OK
SFC write: offset 0x0, size 0x40000
262144 bytes written: OK
reading u-boot.bin
524288 bytes read
SFC erase: offset 0x40000, size 0x80000
OK
SFC write: offset 0x40000, size 0x80000
524288 bytes written: OK
reading env.bin
131072 bytes read
SFC erase: offset 0xc0000, size 0x20000
OK
SFC write: offset 0xc0000, size 0x20000
131072 bytes written: OK
reading vmlinux.ub.gz
3145728 bytes read
SFC erase: offset 0x100000, size 0x300000
OK
SFC write: offset 0x100000, size 0x300000
3145728 bytes written: OK
reading rootfs.arm.jffs2.nand
36276844 bytes read
NAND erase: device 0 offset 0x0, size 0x10000000
Bad block table found at page 262080, version 0x01
Bad block table found at page 262016, version 0x01
Erasing at 0xffe0000 -- 100% complete.
OK
NAND write: device 0 offset 0x0, size 0x2298a6c
36276844 bytes written: OK
** Invalid boot device **
** Skipping rootfs1.arm.jffs2.nand **
** Invalid boot device **
** Skipping var.arm.jffs2.nand **
resetting ...
Starting Microloader ASM built on Jun 19 2014 17:46:39...
Initializing PLLs...
Initializing Clocks..
Initializing DDR PLLs/Clocks...
Initializing DDR controller...
Initializing data section...
Initializing stack ptr...
Switching to 'C' code...
Starting Microloader C...
Chip: SHINER-IP
Found Internal Ethernet PHY on GMAC0....
Checking for Guide button press ...
GCS in ISA MODE
GCS: SFC DEVICE SETUP COMPLETE
Setting up default ATAG list...
Jumping to U-Boot ...
--------------------------------------------------------------------------------
| U-Boot 2009.08-00054-g61c6265 (Jun 11 2014 - 10:49:06) CST HDx |
|------------------------------------------------------------------------------|
| Chipset information |
| Vendor: NXP Type: Shiner-IP Revision: M1 Fuses: 0015726F |
|------------------------------------------------------------------------------|
| Clock information |
| *** not available yet *** |
|------------------------------------------------------------------------------|
| Frontpanel information |
| Vendor: CST Version: 5.1 Display: none |
|------------------------------------------------------------------------------|
| Memory configuration |
| Start | End | Type | Description |
|----------+----------+---------+----------------------------------------------|
| 00000000 | 0FFFFFFF | RAM | System main memory bank #0 (256M) |
| 20000000 | 2FFFFFFF | RAM | System main memory bank #1 (256M) |
| D0000000 | D03FFFFF | S-FLASH | Eon Silicon EN25Q32 ( 4M / 64K x 64) |
*** Warning - bad CRC or SFC, using default environment
| 00000000*| 1FFFFFFF*| NAND | Toshiba NAND 512MiB 3,3V 8-bit |
|------------------------------------------------------------------------------|
| Network configuration |
| MAC: LIP 6300 address: 00-C5-5C-79-31-29 |
--------------------------------------------------------------------------------
Hit any key to stop autoboot: 0
SFC read: offset 0x100000, size 0x300000
3145728 bytes read: OK
## Booting kernel from Legacy Image at 01000000 ...
Image Name: GZIP linux-2.6.34.14 kernel
Image Type: ARM Linux Kernel Image (gzip compressed)
Data Size: 2647632 Bytes = 2.5 MB
Load Address: 00008000
Entry Point: 00008000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Linux version 2.6.34.14 (root@mh) (gcc version 4.7.3 20130102 (prerelease) (crosstool-NG 1.18.0) ) #1 SMP Wed May 14 17:09:22 MSK 2014
[ 0.000000] CPU: ARMv7 Processor [411fc091] revision 1 (ARMv7), cr=10c57c7d
[ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
[ 0.000000] Machine: Entropic STB Apollo platform
[ 0.000000] ChipID=0x3 ChipRevID=0x2
[ 0.000000] EMAC address found in ATAG list ...
[ 0.000000] Mac 0 address bytes = 00:c5:5c:79:31:29
[ 0.000000] Memory policy: ECC disabled, Data cache writealloc
[ 0.000000] Early platform io descriptors mapping...
[ 0.000000] PERCPU: Embedded 7 pages/cpu @80a6c000 s6784 r8192 d13696 u65536
[ 0.000000] pcpu-alloc: s6784 r8192 d13696 u65536 alloc=16*4096
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 129536
[ 0.000000] Kernel command line: noinitrd console=ttyS0,115200n8 mtdparts=nx_sfc:256k@0k(uldr),512k@256k(u-boot),128k@768k(env),128k@896k(spare),-(kernel);nx_2017:256m@0k(root0),32m@256m(var),-(root1) root=mtd:root0 rootfstype=jffs2 rootflags=noatime rw
[ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 256MB 256MB = 512MB total
[ 0.000000] Memory: 247692k/247692k available, 276596k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
[ 0.000000] vmalloc : 0xa0800000 - 0xd0000000 ( 760 MB)
[ 0.000000] lowmem : 0x80000000 - 0xa0000000 ( 512 MB)
[ 0.000000] modules : 0x7e800000 - 0x80000000 ( 24 MB)
[ 0.000000] .init : 0x80008000 - 0x8002f000 ( 156 kB)
[ 0.000000] .text : 0x8002f000 - 0x805ef000 (5888 kB)
[ 0.000000] .data : 0x8060e000 - 0x8063f1a0 ( 197 kB)
[ 0.000000] SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] NR_IRQS:388
[ 0.000000] Initializing Cortex Interrupt Distributer (DISTR) at Vir:0xE0101000 = Phy:0xE0101000
[ 0.000000] Initializing Cortex Generic Interrupt Controller (GIC) at Vir:0xE0100100 = Phy:0xE0100100
[ 0.000000] Initializing Cortex A9 Global Timer at Vir:0xE0100200 = Phy:0xE0100200, using Irq:27, at Freq:250000000
[ 0.000000] GT: clocksource_global->mult = 0x80000000, clocksource_global->shift = 0x1d
[ 0.000000] GT: timer0_clockevent->mult = 0x40000000, timer0_clockevent->shift = 0x20
[ 0.000000] GT: timer_set_mode = 1
[ 0.000000] GT: timer_set_mode = 2
[ 0.000000] Console: colour dummy device 80x30
[ 0.000000] console [ttyS0] enabled
[ 0.010000] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
[ 0.270000] Mount-cache hash table entries: 512
[ 0.270000] CPU: Testing write buffer coherency: ok
[ 0.280000] Calibrating local timer... 249.83MHz.
[ 0.340000] GT: timer_set_mode = 0
[ 0.340000] L310 cache controller enabled
[ 0.340000] l2x0: 8 ways, CACHE_ID 0x410004c4, AUX_CTRL 0x32021001, Cache size: 131072 B
[ 0.350000] Brought up 1 CPUs
[ 0.350000] SMP: Total of 1 processors activated (996.14 BogoMIPS).
[ 0.360000] NET: Registered protocol family 16
[ 0.520000] Adding platform devices...
[ 0.520000] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
[ 0.530000] GMAC0: using internal PHY
[ 0.540000] GMAC0: using MII mode
[ 0.540000] Adding platform i2c devices...
[ 0.540000] SATA: Adjusting los_lvl (rd_val=0x8a46, wr_val=0x8ae6)
[ 0.550000] SATA: Adjusting rx_term_en0/1 (rd_val=0x2750275, wr_val=0x2770277)